Clock data recovery, CDR, loops in serial data transmission links measure the position of the transition between logic states ie. one-to-zero, zero-to-one, or multilevel-transitions. This requires high-speed sampling latches in the receiver front end, a high-speed phase detection logic function and the appropriate clock generation building blocks, e.g. I/Q generator, or multiphase generators. There are two distinct problems associated with that traditional approach. First, both the sampling latches associated with to the measurement of the logic transitions, as well as the phase detector circuits require a significant amount of direct current, DC, power to be operated at high speed. Secondly, the accuracy of the logic transition measurement is prone to errors, e.g. due to latch offsets, different clock wire length, device mismatches etc. At high frequencies, this error is contributing a significant amount of jitter to the jitter budget of a serial link. Many modern serial links are leveraging forward error correction, FEC, codes, e.g. Hamming codes. These codes can typically detect and correct one or more errors in the receiver based on the transmission of a limited number of additional parity bits. In typical serial links, single errors in a reasonable sized stream of bits are dominating.
Forward error correction is a method to improve connection quality in digital communication systems. Forward in conjunction with error correction means the correction of transmission errors at the receiver side without any additional information from the transmitter. The theoretical background of FEC is given by information theory. The main concept of FEC is to add a certain amount of redundancy to the information, which can be exploited by the receiver to correct transmission errors due to channel noise. In the literature FEC coding is therefore often described as channel coding. C. Shannon presented in his mathematical theory of communication, that every transmission channel has a theoretical maximum capacity, called channel capacity, which depends on the bandwidth and the signal-to-noise ratio. The capacity of most implemented systems is much smaller than the maximum possible value suggested by the theory. As a consequence the use of suitable codes will allow further improvement of bandwidth efficiency. A very simple example, which explains the principle of FEC, is the use of repetition coding: if a system transmits every message three times, the receiver is able to correct one corrupted message by a simple majority decision. The coding theory shows, that this method is very ineffective, because the maximum data rate is reduced to one third of the channel data rate. A large variety of more efficient codes have been developed, and the progress in microelectronics has enabled modern communication protocols to implement them in real-time applications.
The error correcting codes can be divided in two main families: block codes and convolutional codes. Block codes add a constant number of parity bits to a block of information bits, whereas convolutional codes generate a modified output bit stream with a higher rate than the input stream. The various codes have different properties with respect to error correction performance and decoding complexity. Additionally, for a real system design factors like block size and scalability should be considered.
When using block codes the data to be transmitted is segmented into blocks of a fixed length k. To each block a certain amount of parity bits are added. The information bits and the parity bits together form the code words of length n. The rate r of a (n, k) block code is defined as r=k/n. Block codes might be separated in two main families: binary and non-binary codes. Examples for binary codes are Cyclic, Hamming, Hadamard, Fire, Golay and BCH codes. The non-binary codes work on symbols consisting of more than one bit. The most popular example are the Reed-Solomon codes, which form are derived from binary BCH codes.
All practically used block codes are linear. This means, that the modulo-2 addition of two code words is also a valid code word. Linear block codes have several properties, which are helpful for practical implementation. The codes can be defined in form of a generator and a parity check matrix. The error syndrome concept can be used to detect and correct errors on the receiver side. More information about the forward error correction can be found in Robert H. Morelos-Zaragoza, “The Art of Error Correcting Coding”, John Wiley & Sons, Apr. 19, 2002.
In FIG. 1 a block diagram of a clock data recovery, CDR, loop according to the prior art is depicted. The receiver 1 comprises a serial data input connected via a preamplifier 2 to a data latch 3 and an edge latch 4, wherein the data latch 3 intermediately stores the value of the sampled input data signal and the edge latch 4 intermediately stores the transition between different logic states. Both the data latch 3 and the edge latch 4 are sampling latches and their outputs are coupled to a block collection unit 8, which converts serial input data to parallel output data. The CDR loop further comprises a phase detection unit 9, which determines by means of the sampled data and edges a phase correction signal Δφ. The phase correction signal Δφ is lead to a loop filer and phase rotator control 10, which generates out of it a control signal ctrl for a phase rotator 5. The phase rotator 5 in turn generates out of the control signal ctrl a first sample clock sclkd for sampling the data and a second sampling clock sclke for sampling the edges. The first sample clock sclkd provides the sampling points for the data latch 3 and the second sampling clock sclke provides the sampling points for the edge latch 4. A further input of the phase rotator 5 is connected to an oscillator 7 and an clock buffer 6, which provide a reference clock refclk. The data collection unit delivers its parallel output data also to an error syndrome calculation unit 11 and a data logic 12. The error syndrome calculation unit 15 is used to detect single errors in the collected input data. Its output is used in the data logic 12 together with the collected data of the block collection unit 8 to allocate n error free parallel data at the output of the data logic 12. Finally, a startup-logic 13 is provided to start-up the data logic 12. The data logic 12 also de-skews and scrambles the data and is used for training. With the help of the training the boundaries of the individual data blocks, of which many are transmitted serially, are determined. The data blocks are connected back-to-back in the serial data stream without explicit boundaries between the data blocks. However, the error syndrome calculation unit 15 requires the bits of each data block to be reordered to their original sequence. This initialization, which can for example be done by transmitting known data patterns during a startup phase, is called training.
In Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, and Mark A. Horowitz, “A variable-frequency parallel I/O interface with adaptive power-supply regulation”, IEEE Journal of solid-state circuits, vol. 35, no. 11, November 2000, p. 1600-1610, a similar CDR loop is depicted.
As noted above, these approaches require several high-speed sampling latches in the receiver front end, a high-speed phase detection logic function, and an appropriate multiphase generator for clock generation. The data latch 3 and the edge latch 4 and the generation of their respective clock signals, as well as the phase detection unit 9 require a significant amount of DC power to be operated at high speed. Furthermore, the accuracy of the logic transition measurement is prone to errors, e.g. due to latch offsets, different clock wire length, device mismatches etc. At high frequencies, this error is contributing a significant amount of jitter to the jitter budget of the serial data link.